Power is a problem with most electronic systems and in particular with memory systems. The continued scaling of CMOS technology has caused standby power dissipation of static random access memories (SRAMs) to become an increasing problem. 6T SRAMs are considered one of the lowest power CMOS circuits and thus power loss is particularly important in these devices. Memory arrays implemented using SRAMs have very few cells active at any given time because READ/WRITE operations on a two-dimensional arrangement of memory cells typically enables one row at a time. Aggressive power management techniques can be employed by partitioning the memory into smaller banks of memory arrays and by collapsing the power supply of unselected memory arrays/rows. These techniques leverage the higher intrinsic stability of the SRAM cell when it is unselected.
The intrinsic stability of a SRAM cell corresponds to a noise-margin of a cross-coupled inverter loop of the cell when it is disconnected from the bit-lines. In contrast, the read stability of the cell corresponds to the noise-margin of the inverter loop with the word-line being ACTIVE and the cell internal nodes being connected to the bit-lines. The read stability is usually worse than the intrinsic stability. Consequently, the power supply can drop to a far lower value than when the cell is read-out.
Powering down the supply can be accomplished by the use of “sleep switches” (or sleep devices) that are deactivated when cells are idled and activated when the cells are being written to or read from. To save the state of the memory array, the power supply of the SRAM arrays should not be allowed to collapse completely.